Up one level (Analog CMOS)
Spice models
HSPICE: (file ending .l)
.LIB setup_blabla
.param blabla1=1
.param blabla1=2
.subckt nch_mine n1 n2 n3 n4 l=length w=width multi='1'
+_dmcg='0.1234' _dmci='0.1234'
.param lef='(l)*scale'
main n1 n2 n3 n4 nch w=w l=l ad=ad as=as pd=pd ps=ps nrd=nrd nrs=nrs m=multi nf=nf sa=sa sb=sb sd=sd sca=sca scb=scb scc=scc delvto=_delvto mulu0=_mulu0
.param ....
.model nch.1 nmos ( level = 54 lmin = '0.1234'
+lmax = 0.1234 wmin = 0.1234)
.model nch.2 nmos ( level = 54 ...)
.ends nch_mine
.ENDL setup_blabla
Spectre: (file ending .scs)
section setup_blabla
parameters blabla1=1
parameters blabla2=1
inline subckt nch_mine (n1 n2 n3 n4)
parameters l=length w=width multi=1
+_dmcg=0.1234 _dmci=0.1234
parameters lef=(l)*scale
nch_mine (n1 n2 n3 n4) nch w=w l=l ad=ad as=as pd=pd ps=ps nrd=nrd nrs=nrs
+m=multi nf=nf sa=sa sb=sb sd=sd sca=sca scb=scb scc=scc delvto=_delvto
+mulu0=_mulu0
parameters ....
model nch bsim4 {
1: type=n
+lmin=0.1234
+lmax=0.1234 wmin=0.1234
2: type=n
..
}
ends nch_mine
endsection setup_blabla
Eldo: (file ending .eldo)
.lib setup_blabla
.param blabla1=1
.param blabla1=2
.subckt nch_mine n1 n2 n3 n4 l=length w=width multi='1'
+_dmcg='0.1234' _dmci='0.1234'
.param lef='(l)*scale'
main n1 n2 n3 n4 nch w=w l=l ad=ad as=as pd=pd ps=ps nrd=nrd nrs=nrs m=multi nf=nf sa=sa sb=sb sd=sd sca=sca scb=scb scc=scc delvto=_delvto mulu0=_mulu0
.param ....
.model nch.1 nmos ( level = 60 lmin = '0.1234'
+lmax = 0.1234 wmin = 0.1234)
.model nch.2 nmos ( level = 54 ...)
.ends nch_mine
.endl setup_blabla
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